Do I understand correctly that you could add this to the
description?
For example, if the banks[16] array contains [2,3,5,7,0,0,0,0,0,...] then that means that memory[0:2] belong to Bank A, memory[2:5] belong to Bank B, memory[5:10] to C, memory[10:17] to D, and memory[17:] aren't in any bank.
If so, that's wild, with wacky implications:
Here is my class description. Does it make at least a little sense to someone who hasn’t spent time with the driver?
"""
The Icom land mobile bank model.
The radio stores bank capacity in an array of 16 bit, unsigned
integers. There is no other mapping. This implies
- memories in a bank are contiguous,
- memories in a bank are in the order that they apear in the
"memory" array,
- each memory can only be in one bank,
- all memories not in a bank are at the end of the "memory" array.
Here, "memory" array refers to the struct in "MEM_FORMAT".
“”"
Do all models look the same in the banks tab? This is what I see:
Thanks for the spelling correction.
On May 24, 2023, at 15:00, Craig Jones via chirp_devel <chirp_devel@intrepid.danplanet.com> wrote:
_______________________________________________I was wondering what "capacity" meant. So, if that's just the count, where is the actual linkage between the bank and the memories? Anyway, the Anytone model I'm working on right now is the same (each mem is limited to one bank, or none):
class AnytoneBankModel(chirp_common.BankModel):"""The Anytone bank model, for the radios that support it, is that a memorychannel can only belong to one bank at a time. There are 10 banks (A-Jwith no alternate names). The mapping is done in a block of bytes thatcorrespond to the 750 memories (one byte per memory). The possible valuesare 0-9 (A-J) or 15 (x0F) for "off"."""def __init__(self, radio, name="Banks", num_banks=10, num_memories=750):super(AnytoneBankModel, self).__init__(radio, name)self._bank_bounds = range(num_banks)self._mem_bounds = range(1, num_memories + 1)self._banks = [chirp_common.Bank(self, i, string.ascii_uppercase[i]) for i in self._bank_bounds]def get_num_mappings(self):return len(self._banks)def get_mappings(self):return self._banksdef add_memory_to_mapping(self, memory, bank):self._radio.set_bank(memory.number, bank.get_index())def remove_memory_from_mapping(self, memory, mapping):self._radio.clr_bank(memory.number)def get_mapping_memories(self, bank):"""Returns a list of all memories assigned to the given bank"""memories = []for i in self._mem_bounds:bank_index = self._radio.get_bank(i)if bank_index is not None and bank_index == bank.get_index():memories.append(self._radio.get_memory(i))return memoriesdef get_memory_mappings(self, memory):bank_index = self._radio.get_bank(memory.number)return [] if bank_index is None else [self._banks[bank_index]]
BTW, "scrabmler_code" is misspelled.
On 5/24/2023 1:52 PM, Joseph Scanlan wrote:
A memory can not be in more than one bank simultaneously. A memory need not be in a bank. Memories are stored sequentially starting from [0]. Each number in banks holds the count of memories in that bank. The count can be 0. So to find the start index of the first memory in a bank we have to sum the sizes of all previous banks.On May 23, 2023, at 14:06, Craig Jones via chirp_devel <chirp_devel@intrepid.danplanet.com> wrote: I just went through that myself. The first two questions: 1. Can one memory belong to multiple banks simultaneously? 2. Does every memory have to belong to at least one bank? The answers determine which base class you use for the bank model. You need to implement a bank model so that Chirp can inquire, for example, which memories are in bank C? You also need to implement get_bank(), set_bank(), clear_bank() for a memory (in the radio class), which will be called by the bank model. Hopefully, that's enough to get you started. On 5/23/2023 1:47 PM, Joseph Scanlan via chirp_devel wrote:Does anyone have an example that will help me understand MemoryMapping, MappingModel, Bank, and BankModel classes? I’m working on a driver for the Icom IC-F520 land mobile radio. The F520 has 256 channels and 16 banks. This is how they look in MEM_FORMAT: struct { u16 capacity; } banks[16]; struct { char name[10]; u32 inhibit:1, freq_rx:31; u32 inhibit_tx:1, freq_tx:31; u8 rx_tone_off:1, rx_tone_digital:1, unk01:6; u8 rx_tone; u8 tx_tone_off:1, tx_tone_digital:1, unk02:6; u8 tx_tone; u8 unk03:3, tot_on:1, lockout_repeater:1, lockout_busy:1, power_rf:2; u8 log_in:2, log_out:2, unk04:1, text_on:1, unk05:1, two_tone_unk1:1; u8 unk06:4, two_tone_unk2:2 auto_reset_a:1, unk07:1; u8 narrow:1, scrambler_on:1, scrambler_inhibit:1, compander_on:1, unk08:4; u8 unk09; u8 scrabmler_code; u16 unk10; u16 unk11; u8 unk12:6, two_tone_index:2; } memory[256]; _______________________________________________ chirp_devel mailing list chirp_devel@intrepid.danplanet.com http://intrepid.danplanet.com/mailman/listinfo/chirp_devel Developer docs: http://chirp.danplanet.com/projects/chirp/wiki/Developers-- This email has been checked for viruses by AVG antivirus software. www.avg.com _______________________________________________ chirp_devel mailing list chirp_devel@intrepid.danplanet.com http://intrepid.danplanet.com/mailman/listinfo/chirp_devel Developer docs: http://chirp.danplanet.com/projects/chirp/wiki/Developers
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